Architecting Silicon.
Bridging the gap between high-level architectural specs and physical silicon realization.
Logic Meets Physicality.
I am a VLSI Design Engineer with a passion for high-performance computing and energy-efficient architecture. With a background in both Frontend RTL and Backend Physical Design, I specialize in navigating the "valley of death" between synthesis and timing closure.
Currently focusing on 3nm nodes and the integration of AI-driven placement tools to accelerate the PPA (Power, Performance, Area) loop.
Professional Cycles
Senior RTL Design Lead
Directing the development of next-gen RISC-V accelerators. Successfully reduced power consumption by 18% through aggressive fine-grained clock gating and operand isolation techniques.
ASIC Design Engineer
Worked on the Tensor Core integration for Hopper architecture. Optimized data-path latency by 10% through custom cell placement and advanced routing constraints.
Verification Intern
Developed UVM agents for LPDDR5 controllers. Achieved 100% functional coverage across all corner cases for the PHY interface.
Engineering Stack
RTL & Logic
- SystemVerilog / Verilog
- High-Level Synthesis (HLS)
- FSM Design & Optimization
- CDC / RDC Analysis
Verification
- UVM / OVM Methodology
- SVA (Assertions)
- Formal Verification (JasperGold)
- Power-Aware Simulation
Physical Design
- Synopsys Fusion Compiler
- Cadence Innovus
- PrimeTime (STA)
- Calibre DRC/LVS
Scripting & Automation
- TCL (Tool Control Language)
- Python for EDA
- Perl Regression Scripts
- Makefiles / Shell
Silicon Portfolio
Project Titan-5
A multi-core SoC taped out on TSMC 7nm, featuring integrated AI accelerators.
Mem-Link v3
Ultra-low latency memory controller designed for 3.2Gbps throughput per pin.
Sub-Zero Logic
Research project exploring superconducting logic gates for quantum-interfacing.
Design Flow
Spec & Architecture
Defining micro-architecture and power domains.
RTL & Verification
Coding and UVM testing for logical correctness.
DFT Insertion
Scan chains and BIST for silicon manufacturability.
Synthesis & STA
Converting to netlist and closing timing constraints.
Physical Layout
Place, route, and sign-off verification (DRC/LVS).